The Cactus in action with its new brass case badge
It started out as an idea.
It's taken a pile of paper and lots of research to get this far. I've spent months of time working on it. I've run digital logic simulations, and revised my designs time and again. I've had help from a handful of friends, plenty of acquaintances, and a smattering of strangers. I've experienced countless failures and setbacks, and sacrificed more sleep than on any previus project I've embarked on. But it's all been worth it.

What's the point of all this?
The Cactus is a computer, built with the goal of recreating the homebrew computer experience of the 1970s. This includes hand-wired circuit boards, 7400-series logic chips, and only a few post-1980 concessions where appropriate. While many machines of that era were commonly found with a front panel interfaces, only a few obscure examples use a 6502 microprocessor. Initially, the Ohio Scientific OSI-300 was the only exception that I'm aware of. However it's purely a 6502 trainer and not intended to perform any sort of practical computing. There is a front panel add-on for the SYM-1 by CGRS Microtech , but it's primarily governed by software from what I can tell. I've also recently learned about a 6502 homebrew design found in Byte Magazine known as the the Kompuutar. I would be surprised if any surviving examples of this machine exist, since they would have all been hobbyist made. All three of these examples are obscure, and didn't achieve much commercial success. Not to mention, they're all bundled with heavy limitations.

It was far more common to find 6502 processors with ROM monitors, hexadecimal keypads, and 7-segment displays, exemplified by the MOS Technology KIM-1, Synertek SYM-1, and Rockwell AIM-65. Then the microcomputer boom of 1977 changed the game entirely, and the front panel's time had come to an end. I've used the modern Mini OSI-300 replica in lieu of a real one. The Mini OSI-300 recreates the experience while upgrading the SRAM from 128 bytes to 4K, all while having a smaller device footprint. The hard part is using such tightly packed switches, and my fingers get tired of it really fast.

Time to build a computer:
The primary CPU/RAM/ROM/UART interactions are based on Grant Searle's Mininal 6502 design, modified for use with a bus structure. Quinn Dunki's Veronica has served as major inspiration, along with a slew of 1970s mini and microcomputers with front panel interfaces. The front panel logic is very much my own original work. It takes about two dozen 74HCT series logic chips to make up the front panel control logic. Previously, I was using a variety of other 7400 series logic families, but switched to HCT at the suggestion of the good folks at The result is a colossal pile of wires that actually runs.

Other modernization choices made include the use of a single SRAM chip containing 32K. The historically accurate solution would have been to use boards and boards of DRAM, or a very tiny quantity of SRAM chips (resulting in a much smaller amount of available RAM). The biggest change is the use of a 65C02S. The CMOS design and static core mean that the registers can be clocked down below 100KHz, unlike the original NMOS versions of the 6502. If you slow the clock down any further than that, your registers may lose thier values. As far as I'm aware, many contemporary microprocessors from the 1970s could be clocked down and not lose thier state in this way. I've also converted my design to use 6551's instead of a 6850 for serial interaction.

There is so much room for improvement in both functionality and construction methods. The wire used is intended for wire wrap sockets, rather than being cut to length and soldered in place. However, this method of construction is time consuming. I would like to get boards manufactured but that's a process that I'm not versed in - yet. There are all kinds of useful software that needs to be written or ported. So much work to do...


Processor: Western Design Center W65C02S @ 1MHz
RAM: 32K Static RAM (62256) & 2K Static Non-Volitile RAM (M48Z12)
ROM: 16K EPROM, 27128
RS232 Serial, MC68B50 at 38400, 19200, 9600, 4800, 2300, 1200, 600, 300, 150, or 75 baud
or Dual R6551 at 19200, 9600, 7200, 4800, 3600, 2400, 1800, 1200, 600, 300, 150, 134, 109, 75, or 50 baud
16 bits of Parallel I/O from 65C22 VIA
OSI BASIC Version 1.0 Rev 3.2 from 1977
Direct Memory Access via front panel.

Things I would like to add:
Perfecting single step control & possibly an adjustable slow clock.
A useful ROM monitor, to manipulate memory from a terminal.
More complex user I/O from 65C22 VIA.
Video output from an MC6845 CRTC or 6560 VIC chip. Far down the line.
Sound output -- not sure from what yet. If I could make an SAA-1099 work this slow, I would. That, or the 6560's internal sound output.
Audio cassette tape storage. It's not a reliable or practical storage method, but it is very 1970s.
Maybe an MC6800 CPU board?
Core Memory. I realize just how complicated this would be, but I want to try.
Diode-matrix ROM just to say I did.

Memory Map:

0000-7FFF 32K RAM
8000-9FFF Unallocated (8K)
A000-A3FF Serial Interfaces
A400-A5FF Unallocated
A600-A7FF Parallel Interface
A800-B7FF Unallocated

BFFF Serial configruation byte while using 6551 ACIA
FE00-FF77 Serial routines

What I'm working on right now:
As of July 2018, I'm assembling a few boards, and writing software in 6502 machine language. I've built a simple 6522 board, and it's being tested with a modern CMOS 65C22. I've added a bank of 8 software-controlled LED, and another bank of headers. My next upgrade will involve 8 software-accessable switches, because "kill the bit" on Altair and IMSAI machines has demonstrated to me the merits of including such a feature. I think it's within the realm of possibillity to use the existing data control switches to this end. Having 8 addressable LEDs for debugging has been essential for debugging purposes.

6522 VIA board Backside of the front panel

I'm also testing a new serial board that uses two 6551 ACIA's with MAX232 level shifters all on a single card. Due to the significantly reduced part count for baud rate selection, I was able to fit the second serial port I've desired for some time. At present, I've got one of the ACIA's functional, and have modified the serial routines for BASIC to utilize the new chip. The user can now change the baud rate in software, rather than physically moving a jumper

Testing the LED bank

Lastly, I've been curious about running the Cactus with an authentic NMOS 6502 manufactured by Commodore. This means additional buffers are required for the address and data buses during front panel interaction. However, the nature of the internal registers will limit the functionality with this microprocessor variant. Slow clock modes, single stepping, and stopping the CPU expecting to resume on a human timescale will be out of the question with this board, but the original CMOS board will still have these capabilities.

The Cactus in action, running BASIC, with its older case badge.

Running BASIC The front panel

The heart and soul of the Cactus: the 35 pin backplane, and the 7 primary cards.

Top row: RAM card, EPROM card, serial card, address control card (rev 1)
Bottom row: CPU card, status control card, data control card

The heart of the machine The magnificent seven boards

Front Panel Logic & Controls

Over half of the Cactus's integrated circuitry is dedicated to operating the front panel independently from the 6502. It's divided into three main cards:
Address Control allows the user to select an address to visit using the 16 silver toggle switches. After selecting an address, the user can either see what data is located there using Examine, or they can increment the current address just by using the Examine Next switch. This time saving measure is complemented by the Deposit Next switch for serious data entry.

Data Control allows the user to see whatever data is contained at the selected address. However, the data bus is not directly wired to the status lights. Instead, a series of interlocking buffers are used to load that value into a series of flip-flops, used as a temporary workspace. From there, the user can modify a byte, one bit at a time using SET & CLEAR momentary switches. When the user has finished entering a new byte or modifying an existing byte, pressing Deposit will allow that byte to pass back to the data bus and overwrite the previous value in RAM. This allows the user to fix off-by-one errors with greater ease. While the microprocessor is in control, the data bus is directly visible on the data indicators.

Status Control allows the user to control complex operations of the machine. The Address & Data control card functions are both orchestrated by the Status Control card, to ensure that each operation happens in the correct order. Many of the direct memory access safety interlocks are controlled from here.

Watch the Cactus during an earlier stage of development:

So many wires, so many tests...
Backside of the front panel Testing the RAM card

The Cactus was on display at Vintage Computer Festival East XIII in Wall, NJ on May 19 & 20, 2018.

I explained why I built it, what motivations lead it its design choices, and where the project was headed. Visitors were welcome to try using the front panel, program in BASIC, and listen to me ramble. I used a Heathkit H89 as a serial terminal to program using BASIC. A friend connected up a dot matrix printer in parallel with the terminal, and also managed to copy over Lunar Lander one line at a time from my Toshiba Libretto 70CT. Playing games on the Cactus!

I also briefly replaced the 1MHz clock crystal with an external pulse generator. The system clock was brought down into the sub-100KHz range, going as low as a few dozen Hz at times just for fun. I garuntee you've never seen a 6502 move that slowly. BASIC runs really slowly at that speed, and it gives you some perspective on how much work is happening in such a brief moment in time within the 6502.

A friend filmed the Cactus while I had external pulse generator connected. You can see individual instructions go by on the indicators as it struggles to begin rendering text on my H89:

My exhibit!

Lunar Lander Front panel running

People learning about the Cactus

Despite not actually being a vintage computer, it was a major hit with visitors and fellow exhibitors. Quite frankly, I wasn't expecting such an overwhelmingly positive response. I'm glad that people enjoy what I have built. I've been asked several times over if I'm planning to make a kit. Please be patient, because I've got alot of work to do before we're ready for anything like that. That being said, I'm talking with friends who have produced and sold kits about what's involved to see how feasible such a venture is.

Want to see the Cactus in person?

Vintage Computer Festival West 13

I exhibited the Cactus at VCF West on August 4th & 5th in Mountain View California, at the Computer History Museum. Details, photos, and possibly video to follow. I had alot of fun!

DEFCON 26 Hardware Hacking Village

I gave a talk & demonstration at the DEFCON 26 HHV at 4PM on August 11th. I discussed the history of the front panel and 6502's, my design influences, and demonstrated the machine in action. I was really happy with the level of interest on display by attendees. Photos to follow!

Vintage Computer Festival Midwest 13

I will be exhibiting the Cactus and giving a talk at VCF Midwest is September 15th & 16th in Elk Grove Village, Illinois. The talk will be held on Sunday at 1PM.

Have a question? Want to know more about the Cactus? Know of another 6502 machine with a front panel? Email me:


This page was last updated on 8-13-2018