The Project: Motivations Specifications Current Focus Front Panel Logic Cards Project Logs Events: VCF East XIII VCF West XIII DEFCON 26 VCF Midwest 13 VCF East XIV VCF West XIV VCF Midwest 14 The Future: Want a Cactus? |
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It started out as an idea.
It's taken a pile of paper and lots of research to get this far. I've spent months of time working on it. I've run digital logic simulations, and revised my designs time and again. I've had help from a handful of friends, plenty of acquaintances, and a smattering of strangers. I've experienced countless failures and setbacks, and sacrificed more sleep than on any previous project I've embarked on. But it's all been worth it.
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What's the point of all this?
The Cactus is a computer, built with the goal of recreating the homebrew computer experience of the 1970s. This includes hand-wired circuit boards, 7400-series logic chips, and only a few post-1980 concessions where appropriate. While many machines of that era were commonly found with a front panel interface, only a few obscure examples use a 6502 microprocessor. Initially, the Ohio Scientific OSI-300 was the only exception that I was aware of. I first saw one at Vintage Computer Festival East X in 2015, at Bill Dromgoole's exhibit table, and it sparked a wave of curiosity and possibility -- but back to reality. The OSI-300 was never intended to perform any sort of practical computing. Rather, it was a bare-bones trainer to introduce the user to the 6502 opcodes.
This is certainly not the only 6502 front panel computer in existence. There is a variant of the CGRS Microtech System 6000 which is an S-100-compatible system that had an optional front panel DMA board. I previously thought this was intended for a SYM-1, or another CGRS Microtech S-100 option, but it's more like a stand-alone system. I've also learned about a 6502 homebrew design found in Byte Magazine known as the the Kompuutar. I would be surprised if any surviving examples of this machine exist, since they would have all been hobbyist made. All three of these examples are obscure, and didn't achieve much commercial success. Not to mention, they're all bundled with heavy limitations.
It was far more common to find 6502 processors with ROM monitors, hexadecimal keypads, and 7-segment displays, exemplified by the MOS Technology KIM-1, Synertek SYM-1, and Rockwell AIM-65. Then the microcomputer boom of 1977 changed the game entirely, and the front panel's time had come to an end. Graphical interfaces with keyboards became the norm, but I digress. I've used the modern Mini OSI-300 replica in lieu of a real one. The Mini OSI-300 recreates the experience while upgrading the SRAM from 128 bytes to 4K, all while having a smaller device footprint. The hard part is using such tightly packed switches, and my fingers get tired of it really fast.
Time to build a computer:
The primary CPU/RAM/ROM/UART interactions are based on Grant Searle's Mininal 6502 design, modified for use with a bus structure. Quinn Dunki's Veronica has served as major inspiration, particularly in her approach to construction and single step operation experiments . I took inspiration on front panel operation and interface design from slews of 1970s minis and micros. The front panel logic is very much my own original work. It takes about two dozen 74HCT series logic chips to make up the front panel control logic. Previously, I was using a variety of other 7400 series logic families, but switched to HCT at the suggestion of the good folks at 6502.org. The result is a colossal pile of wires that actually runs.
Other modernization choices made include the use of a single SRAM chip containing 32K. The historically accurate solution would have been to use boards and boards of DRAM, or a very tiny quantity of SRAM chips (resulting in a much smaller amount of available RAM). The biggest change is the use of a 65C02S. The CMOS design and static core mean that the registers can be clocked down below 10KHz, unlike the original NMOS versions of the 6502. If you slow the clock down any further than that, your registers may lose their values. Some folks may tell you that 100KHz is the slowest an NMOS 6502 should go, but I've seen them clocked much slower and run perfectly fine. Circuitry intending to single step an NMOS 6502 must maintain clock speed while delaying the processor using logic involving the Ready and Sync lines. Further experiments into single step operation of the NMOS processor have taken precidence over the CMOS. I've also tried using 6551's instead of a 6850 for serial interaction for some experiments. However, the 6850 remains the primary ACIA choice for the project.
Construction Methods:
The boards are constructed by point-to-point soldering kynar wire used for wirewrap to standard sockets. Each wire is cut roughly to length by hand, using a pre-cut size where possible, but usually with a bit of slack. Wirewrap sockets were considered both too expensive to buy, and too tall to fit into a compact backplane. Wire is run along the top of the board on the same side as the components to avoid accidental damage to the insulation, but also to keep the soldering area free of obstructions. Some cards for driving the front panel feature a few flywires that travel to other front panel logic cards, rather than travelling on the common C-35 bus. Front panel switches are soldered to 16-position rainhow ribbon cables with IDC termination. The cable harnesses are split into groups of 8 signals, and plugged into pin headers on the front panel logic cards. All chips are socketed, and almost every chip has a decoupling capacitor. Almost. Cards use 7x 5-position right-angle female connectors to connect to the common C-35 bus. Each card is designed to fulfill a specific function where possible to make debugging easier.
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However, this method of construction is time consuming. After a few years of having this project on pause, and learning the basics of Kicad and PCB design, I have been converting my designs into proper PCBs.
There is all kinds of useful software that needs to be written or ported. So much work to do, but it's progressing.
To that end, here's a list of...
Things I would like to add:
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Specifications:
Processor: MOS 6502 @ 1MHz or Western Design Center W65C02S @ 1MHz RAM: 32K Static RAM (62256) & 2K Static Non-Volitile RAM (M48Z12) ROM: 16K EPROM, 27128 RS232 Serial, MC68B50 at 38400 to 75 baud or Dual R6551 at 19200 to 50 baud 16 bits of Parallel I/O from 65C22 VIA SAA-1099 Sound Chip 32x32 Monochrome Text Composite Video OSI BASIC Version 1.0 Rev 3.2 from 1977 Direct Memory Access via front panel |
Memory Map:
0000-7FFF 32K RAM 8000-9FFF Unallocated (8K) A000-A1FF Primary Serial Interface A200-A3FF Secondary Serial Interface A400-A47F Sound Output A480-A5FF Unallocated (383 bytes) A600-A7FF Parallel Interface A800-A8FF Glitchbus Adapter A900 Software Front Panel I/O A901-AFFF Unallocated (1790 bytes) B000-B3FF Video RAM (Text, 1K) B400-B7FF Unalocated (1K) B800-BFFF 2K NVRAM C000-FFFF 16K EPROM ROM Contents: BFFF Serial configruation byte while using 6551 ACIA C000-DED3 OSI BASIC E000-E29C EWOZ Monitor FE00-FF77 Serial routines |
C-35 Bus Layout
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O̅verbar: Active Low Signal Green: Data Bus Yellow: Control Bus Red: Power White: Address Bus | |
| Pin | Function |
| 1 | Data 7 |
| 2 | Data 6 |
| 3 | Data 5 |
| 4 | Data 4 |
| 5 | Data 3 |
| 6 | Data 2 |
| 7 | Data 1 |
| 8 | Data 0 |
| 9 | I̅RQ |
| 10 | N̅MI |
| 11 | R/W̅ |
| 12 | P̅rotect |
| 13 | Run/H̅alt |
| 14 | S̅tep |
| 15 | R̅eset |
| 16 | CPU Assert |
| 17 | Φ2 |
| 18 | 5V |
| 19 | Ground |
| 20 | Address 0 |
| 21 | Address 1 |
| 22 | Address 2 |
| 23 | Address 3 |
| 24 | Address 4 |
| 25 | Address 5 |
| 26 | Address 6 |
| 27 | Address 7 |
| 28 | Address 8 |
| 29 | Address 9 |
| 30 | Address 10 |
| 31 | Address 11 |
| 32 | Address 12 |
| 33 | Address 13 |
| 34 | Address 14 |
| 35 | Address 15 |
Front Panel Control Card Theory Of Operation
Over half of the Cactus's integrated circuitry is dedicated to operating the front panel independently from the 6502. It's divided into three main cards:Address Control allows the user to select an address to visit using the 16 silver toggle switches. After selecting an address, the user can either see what data is located there using Examine, or they can increment the current address just by using the Examine Next switch. This time saving measure is complemented by the Deposit Next switch for serious data entry.
Data Control allows the user to see whatever data is contained at the selected address. However, the data bus is not directly wired to the status lights. Instead, a series of interlocking buffers are used to load that value into a series of flip-flops, used as a temporary workspace. From there, the user can modify a byte, one bit at a time using SET & CLEAR momentary switches. When the user has finished entering a new byte or modifying an existing byte, pressing Deposit will allow that byte to pass back to the data bus and overwrite the previous value in RAM. This allows the user to fix off-by-one errors with greater ease. While the microprocessor is in control, the data bus is directly visible on the data indicators.
Status Control allows the user to control complex operations of the machine. All of the status control switches are momantaries, with accompanying flip-flops or debounce circuitry. The Address & Data control card functions are both orchestrated by the Status Control card, to ensure that each operation happens in the correct order. Sequencing is governed by a logic chain of cascading D-latches clocked from a 555 timer. Many of the direct memory access safety interlocks are controlled from here.
Front Panel Status Control Switches
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